1. Field of the Invention
The present invention relates to a manufacturing method for a semiconductor device, and relates more particularly to a manufacturing method for a semiconductor device having a multilayer interconnect.
2. Description of the Related Art
With the progress in miniaturization and integration of semiconductor devices, the number of interconnect layers has steadily increased. This has resulted in the number of processes required to form the wiring layers and the contact layers for electrically interconnecting the wiring layers accounting for a larger percentage of the total number of manufacturing processes needed for semiconductor device manufacture. The method of forming the wiring layers and contact layers thus occupies an extremely important position in the overall semiconductor device manufacturing process.
One technique for easily and simultaneously forming wiring and contact layers is the dual damascene method. The technique that is taught in Japanese Unexamined Patent Application (kokai) 8-17918 is described below as an example of this dual damascene method.
Typical steps in the production of a wiring layer and contact layer using this dual damascene method are shown in FIG. 11 to FIG. 13.
Referring first to FIG. 11, a first insulation layer 120 is formed on a silicon substrate 110 in which a diffusion layer 112 is formed. A silicon nitride layer 130 is then formed over the first insulation layer 120, and a resist layer R1 is formed over the silicon nitride layer 130. There is an opening 170 in the resist layer R1 above a spot where a contact hole 150, further described below, is to be formed. The silicon nitride layer 130 is then etched.
Referring next to FIG. 12, after the resist layer R1 is removed, a second insulation layer 140 is formed over the silicon nitride layer 130 and first insulation layer 120. Another resist layer R2 is then formed on this second insulation layer 140. There is an opening 180 in this resist layer R2 positioned at the area where a trench 152, further described below, is to be formed. The second insulation layer 140 is then etched using the resist layer R2 as a mask to form a trench 152, and the first insulation layer 120 is etched using the silicon nitride layer 130 as a mask to form a contact hole 150.
After first removing the resist layer R2, the contact hole 150 and trench 152 are then filled with a conductive material so as to cover all surfaces thereof. See FIG. 13. The surface is then polished using a chemical-mechanical polishing (CMP) technique to form an embedded wiring layer 160.
It will be appreciated from the above description that a silicon nitride layer 130, which functions as a mask for etching the first insulation layer 120, must be disposed between the first insulation layer 120 and second insulation layer 140 in order to form contact hole 150 and trench 152 with the above method. When a silicon nitride layer 130 is disposed between the first insulation layer 120 and second insulation layer 140, a resistance-capacitance (RC) line delay occurs as a result of the high dielectric constant of the silicon nitride layer 130. That is, a delay in signal transmission occurs because of an increase in line resistance and an increase in line capacitance. The presence of an RC line delay leads to various problems, including a drop in the processing capacity (e.g., speed) of the semiconductor device, operational errors resulting from cross-talk, and an increase in temperature (heat output) in conjunction with an increase in power consumption.
Therefore, it is an object of the present invention to overcome the aforementioned problems.
A more particular object of the present invention is to resolve the above noted problems by providing a semiconductor device having good electrical characteristics, and by providing a manufacturing method for such semiconductor device.
To achieve these objects, the present invention provides a method for manufacturing a semiconductor device having a plurality of wiring layers, and an insulation layer intervening between wiring layers, and comprises the following steps:
(A) forming an insulation layer on a first wiring layer;
(B) forming in a top part of the insulation layer a wiring trench in an area where a second wiring layer will be formed, and forming in a bottom part of the insulation layer a through-hole in an area where a contact layer for electrically connecting the second wiring layer and first wiring layer will be formed; and
(C) filling a conductive material into the wiring trench and through-hole to integrally form the second wiring layer in the wiring trench with the contact layer in the through-hole.
Step (B) in this method includes the following steps:
(a) forming on the insulation layer a first mask layer having an opening located above an area where the wiring trench is to be formed; and
(b) forming a second mask layer over the first mask layer and insulation layer. This second mask layer has an opening above an area where the through-hole is to be formed. Also, the etching rate of the second mask layer is different from the etching rate of the first mask layer.
(c) etching the insulation layer using the second mask layer as an etching mask; and
(d) etching the insulation layer using the first mask layer as an etching mask.
This semiconductor device manufacturing method of the present invention can thus form a wiring trench and through-hole without disposing a silicon nitride layer between insulation layers. More specifically, by etching the insulation layer using the second mask layer as the mask for etching, a trench patterned identically to the through-hole is formed in the upper part of the insulation layer. The first mask layer is then used as the mask for further etching the insulation layer while maintaining the same trench shape, thereby automatically forming a through-hole and wiring trench aligned with each other.
By thus forming a wiring trench and through-hole without a silicon nitride layer intervening between insulation layers, the step of forming such a silicon nitride layer can be omitted.
A semiconductor device resulting from this manufacturing method does not have a silicon nitride layer intervening between insulation layers. As a result, the dielectric constant between a first wiring layer and second wiring layer can be held to that resulting only from the insulation layer between wiring layers. The RC wiring delay can therefore be kept to the absolute minimum.
The step (C) above preferably includes polishing and planarizing the conductive material by a chemical-mechanical polishing (CMP) after filling the conductive material into the wiring trench and through-hole to integrally form the second wiring layer and contact layer.
The material used for the first mask layer is not limited to a specific material, but is preferably an inorganic material. When the first mask layer is an inorganic material, the inorganic material is preferably a silicon nitride or a silicon dioxide. By using a silicon nitride or a silicon dioxide as the inorganic material, the first mask layer can be used as a stopping layer when the conductive material is polished using a CMP technique.
Yet further preferably steps (c) and (d) are performed in an uninterrupted sequence.
Yet further preferably step (c) includes removing the second mask layer simultaneously with the insulation layer etching. In other words, the etching process removes both the mask layer and the insulation layer. By removing the second mask layer simultaneously with etching the insulation layer, a separate step for removing the second mask layer can be omitted. It is also possible to control the depth ratio between the through-hole and wiring trench in the insulation layer by controlling, for example, the selection of the material for the second mask layer and insulation layer etching, and the shape of the second mask (particularly the height).
The etching rate of the second mask layer depends upon the desired depth ratio between the through-hole and wiring trench, but is preferably in the range of 1000 xc3x85/min to 8000 xc3x85/min, and even more preferably in the range of 2000 xc3x85/min to 3000 xc3x85/min. The height (film thickness) of the second mask layer is preferably in the range 3000 xc3x85 to 9000 xc3x85.
With consideration given to the ease of patterning, the second mask layer is yet further preferably an organic material, such as a photoresist. If the second mask layer is made from an organic material, the etchant used for etching in step (c) above is preferably a mixed gas containing a CF gas. The CF gas is further preferably one or more of the following: CF4, CHF3, C2F6, C4F8, and C5F8. Yet further preferably, the mixed gas containing a CF gas contains at least one of the following: CO, Ar, O2, and N2.
Yet further preferably, the conductive material contains at least aluminum or copper.
A semiconductor device produced by a manufacturing method of the present invention has a plurality of wiring layers and an insulation layer present between the wiring layers, and comprises a trench in at least one insulation layer. This trench is stepped, and has a wiring trench formed in a top part of the insulation layer, and a through-hole in a bottom part of the insulation layer so as to expose a surface part of a first wiring layer. A second wiring layer is further formed in the wiring trench, and a contact layer is formed in the through-hole, by filling the trench and through-hole with a conductive material.
The angle formed by the bottom of the wiring trench and the side wall of the through-hole at the stepped part of the trench is substantially a right angle.
It should be noted that the first wiring layer in a semiconductor device according to this invention includes a first, second, or subsequent wiring layer, or a conductive part of a semiconductor element such as a gate electrode or diffusion layer formed on a substrate surface.
Other objects and attainments together with a fuller understanding of the invention will become apparent and appreciated by referring to the following description and claims taken in conjunction with the accompanying drawings.